The present invention relates to a bit line control decoder circuit, a virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and a data read method of the virtual ground type nonvolatile semiconductor storage device.
In recent years, flash memory capacity is being increased according to the functional development of portable telephones and the expansion of uses on the market of memory cards and files, and devices of small effective cell areas, such as a multi-valued system and a virtual ground array system have successively been developed in order to cope with cost reduction. In particular, the virtual ground array system, which can achieve a small cell area by devising a circuit thereof, permits the development of a device of a small chip area through the same processes. However, because of the virtual ground structure, there cannot be ignored a leak current (properly referred to generically as a xe2x80x9cleak current to the adjacent cellxe2x80x9d) from the memory cell subjected to read (this is referred to as a xe2x80x9cread cellxe2x80x9d) to the cell (this is referred to as an xe2x80x9cadjacent cellxe2x80x9d) located adjacent to the cell or from the adjacent cell to the read cell, and various devices are needed to achieve high-speed read.
In order to improve the aforementioned problem, Japanese Patent Laid-Open Publication Nos. HEI 3-176895 and HEI 6-68683 propose virtual ground array read methods.
FIG. 10 shows the construction of the virtual ground type memory array of an EPROM disclosed in Japanese Patent Laid-Open Publication No. HEI 3-176895. A memory cell 10 is constructed of the well-known electrically programmable insulated gate n-channel field-effect transistor. Each memory cell 10 has a control gate connected to a row line 15, a source region connected to a source column line 12 and a corresponding drain region connected to a drain column line 13. In this figure, the source column line 12 and the drain column line 13 are buried bit lines formed of a diffusion region.
When a memory cell 10b is selected from this memory array to read the contents, the selection is performed by boosting a row line 15a to a positive high potential and concurrently grounding a source column line 12b via a transistor 18. The other drain column lines 13b and so on located on the right-hand side of the source column line 12b remain floating. A read drain bias potential (DRB) supplied to a circuit point 19 is applied via a transistor 17 to a drain column line 13a. A drain bias voltage (RDP) supplied to a circuit point 22 is applied via a transistor 20 to a source column line 12a connected to an adjacent cell 10a. The other source column lines 12 and so on located on the left-hand side of the source column line 12a remain floating.
The value of the read drain bias potential RDP supplied to the circuit point 22 is equal to the potential DRB supplied to the circuit point 19, both being, for example, 1.2 [V]. By supplying the same voltage, a read current wholly flows through the read cell 10b without branching into the adjacent cell 10a. By thus preventing the leak current to the adjacent cell, high-speed access is achieved.
FIG. 11 shows the construction of a virtual ground type memory array disclosed in Japanese Patent Laid-Open Publication No. HEI 6-68683. In this memory array, diffusion wiring lines 1 through 9 operate as diffusion virtual ground lines and diffusion bit lines arranged alternately. The gate wiring lines 10, 11, 12, 13, 20 and so on are formed in a direction perpendicular to the diffusion wiring lines 1 through 9. A metal bit line 30 is provided every two diffusion bit lines, and bit line selecting NMOS transistors 103 and 104 are provided for the connection of the lines. Moreover, one metal virtual ground line is provided every two adjoining diffusion virtual ground lines, and diffusion virtual ground line selecting transistors 51, 52, 53, 61, 62 and 63 are provided for the connection of the lines. In addition, precharge select circuits 70 and 71 are provided.
When a memory cell 101 is selected from this memory array to read the contents, the diffusion virtual ground line select line 12 and the diffusion bit line select line 10 are first pulled up to Vcc simultaneously with the word line, and the diffusion virtual ground line select line 13 and the diffusion bit line select line 11 are made to have the ground level. At this time, only the metal virtual ground line 201 is pulled down to the ground level, and all the other metal virtual ground lines are made to have a precharge level Vpc. Consequently, the diffusion virtual ground lines 6 and 7 come to have the ground level, and the other diffusion virtual ground lines 5, 8 and 9 come to have the Vpc level. Moreover, with regard to the metal bit lines, a metal bit line 302 is selected by a Y-gate 24. Then, a select signal BSR of the diffusion bit line select line 10 is set at the Vcc level, and a select signal BSL of the diffusion bit line select line 11 is set at the ground level, therefore bringing about a state in which the diffusion bit line 3 is selected. Consequently, the diffusion virtual ground line 8 of the adjacent cell 102 is precharged with Vpc. In the above-mentioned manner, the leak current from the diffusion bit line 3 of the read cell to the adjacent cell 102 is suppressed.
In order to further increase the integration density, the virtual ground type memory array is constructed so that an identical diffusion bit line of one block is connected to the largest possible amount of memory cells. Moreover, in order to increase the capacity of the block select transistor to increase the reading speed, there is adopted a method for connecting the diffusion bit lines to the select transistors alternately into different directions every bit line for the provision of transistors of the largest possible size. In the above-mentioned array construction, the diffusion bit line resistance largely varies depending on the location in the array, and the drain voltage during read also causes a voltage drop depending on the location in the array.
FIG. 6 shows an example in which the drain of the read cell is located farthest from the block select transistor. Assuming that a memory cell MCn4 enclosed by a circle is the read cell, then a voltage Vread is applied to a bit line MBL4 connected to the drain. Moreover, a voltage Vdb equal to Vread is applied to a bit line MBL3 connected to the drain of an adjacent cell MCn3 in order to prevent the leak current. In this case, the read cell MCn4 is located farthest from the block select transistor TB4, and therefore, the bit line voltage Vread causes a voltage drop due to a bit line resistance Rd. However, the adjacent cell MCn3 is located nearest to the block select transistor TB3, and therefore, the bit line voltage Vdb is supplied to the drain of the adjacent cell MCn3 without causing a voltage drop. As a result, there is substantially achieved a relation of Vdb greater than Vread. Therefore, current inflow from the bit line of the adjacent cell MCn3 occurs when the adjacent cell MCn3 is in the ON-state, causing a current reduction at the read node. In the worst case, even when the read cell MCn4 is in the ON-state, there occurs misread that the cell is determined to be in the OFF-state.
As described above, in the conventional system, a voltage difference still occurs between the drain voltage of the read cell and the drain voltage of the adjacent cell, as a consequence of which a leak current flows into the read node depending on the state of the adjacent cell or a current flows from the read node to the adjacent cell. This possibly causes misread. Moreover, there is a problem that high-speed read is prevented by the leak current toward the adjacent cell even before the occurrence of misread.
Accordingly, it is an object of this invention to provide a virtual ground type nonvolatile semiconductor storage device capable of effectively suppressing the leak current to the adjacent cell and thereby achieving high-speed read and a data read method for the virtual ground type nonvolatile semiconductor storage device.
Another object of this invention is to provide a bit line control decoder circuit appropriate for the virtual ground type nonvolatile semiconductor storage device described above.
In order to achieve the aforementioned objects, according to one aspect of this invention, there is provided a virtual ground type nonvolatile semiconductor storage device, which has a plurality of nonvolatile memory cell transistors arranged in a matrix form, a plurality of word lines for performing row selection and a plurality of bit lines for performing column selection and in which a source region and a drain region of one memory cell transistor are formed in common with a drain region of a memory cell transistor located adjacently on one side in a direction of row and a source region of a memory cell transistor located adjacently on the other side in the direction of row, respectively, and the source and drain regions formed in common, are connected to the bit lines, the virtual ground type nonvolatile semiconductor storage device comprising:
means for applying a ground potential to the bit line connected to the source region of one memory cell transistor to be subjected to read during read;
means for applying a read drain bias potential to the bit line connected to the drain region of the one memory cell transistor;
means for putting the bit line connected to a drain region of a first adjacent memory cell transistor located adjacently on the other side in the direction of row of the one memory cell transistor into a floating state; and
means for applying a potential equal to the read drain bias potential to the bit line connected to a drain region of a second adjacent memory cell transistor located adjacently on the other side in the direction of row of the first adjacent memory cell transistor.
In the virtual ground type nonvolatile semiconductor storage device of this invention, the potential equal to the read drain bias potential is applied to the bit line connected to the drain region of the second adjacent memory cell transistor during the read operation. The bit line connected to the drain region of the first adjacent memory cell transistor is in the floating state, and therefore, the drain region of the first adjacent memory cell transistor is precharged with the potential equal to the read drain bias potential. Therefore, the leak current from the drain node of the read cell to the adjacent cell is effectively suppressed.
Moreover, lately for the achievement of a high integration density, it is a frequent practice to constitute a block of a plurality of memory cells connected to the bit line (constructed of a diffusion region), interposingly providing a block select transistor at the end portion of each bit line alternately in the direction of row and apply a potential via the block select transistor. In this case, the read cell and the second adjacent memory cell transistor (this being properly referred to as a xe2x80x9csecond adjacent cellxe2x80x9d) are supplied with the potential from the same side in the direction of column. Therefore, the bit line resistance of the read cell and the bit line resistance of the second adjacent cell are substantially the same regardless of the location of the read cell in the array. Therefore, according to the present invention, the potential of the drain region of the read cell and the potential of the drain region of the second adjacent cell substantially become the same during the read operation. Furthermore, the drain region of the first adjacent memory cell transistor (this being properly referred to as a xe2x80x9cfirst adjacent cellxe2x80x9d), which is also in the floating state, is therefore precharged with the potential equal to that of the drain region of the read cell and the drain region of the second adjacent cell. Therefore, the leak current from the drain node of the read cell to the first adjacent cell is suppressed regardless of the location of the read cell in the array. Therefore, high-speed read can be achieved in comparison with the conventional case.
In one embodiment, the bit line connected to the drain region of the first adjacent memory cell transistor is put into the floating state after being precharged.
In the virtual ground type nonvolatile semiconductor storage device of this one embodiment, the bit line connected to the drain region of the first adjacent cell is put into the floating state after being precharged. Therefore, the drain region of the first adjacent cell is more rapidly precharged to the potential equal to that of the drain region of the read cell and the drain region of the second adjacent cell. Therefore, the drain node of the read cell can be precharged at higher speed, and more rapid read can be achieved.
One embodiment comprises a sense amplifier, which executes sense amplification upon receiving an input corresponding to a potential change of the bit line connected to the drain region of the one memory cell transistor to be subjected to read; and
a current-to-voltage converter, which converts a change in a current that flows between the source and the drain of the memory cell transistor into a voltage change and inputs the voltage change into the sense amplifier, while suppressing the potential change of the drain region of the memory cell transistor.
In this one embodiment, during the read operation, the current-to-voltage converter converts the change in the current that flows between the source and the drain regions of the read cell into the voltage change. This sense amplifier executes the sense amplification upon receiving this voltage change as an input. In this case, the current-to-voltage converter suppresses the potential change in the drain region of the read cell even when the read cell is in the ON-state (in the low threshold value state). Therefore, almost no potential difference is generated between the drain node of the read cell and the drain node of the first adjacent cell. Therefore, the leak current from the first adjacent cell to the read cell is suppressed, and high-speed read can be achieved.
In one embodiment, the plurality of memory cells arranged in a direction of column constitute a block;
a block select transistor is interposedly provided at an end portion of each bit line arranged for each block alternately in the direction of row, and
the block select transistor arranged on one side in the direction of column and the block select transistor arranged on the other side in the direction of column of the block are turned on and off by two control signals, which are mutually different every other line in the direction of row.
In the virtual ground type nonvolatile semiconductor storage device of this one embodiment, during the read operation, the block select transistors connected to the source region and the drain region of the read cell are each turned on. The block select transistor connected to the drain region of the first adjacent cell is turned off, while the block select transistor connected to the drain region of the second adjacent cell is turned on. By this operation, the read cell is read.
In this case, the block select transistor connected to the drain region of the first adjacent cell can be put into the OFF-state during the precharge operation. Therefore, the load capacity of the bit line connected to the drain region of the first adjacent cell becomes owned by only the portion (sub-bit line) arranged in the block. Therefore, the drain node of the first adjacent cell can be precharged very rapidly in comparison with the case where the load capacity of the main bit line (portion that belongs to the bit line and corresponds to the potential supply side of the block select transistor) is added.
Furthermore, according to another aspect, there is provided a dedicated bit line virtual ground type nonvolatile semiconductor storage device, which has a plurality of nonvolatile memory cell transistors arranged in a matrix form, a plurality of word lines for performing row selection and a plurality of bit lines for performing column selection and in which a source region and a drain region of one memory cell transistor are formed in common with a source region of a memory cell transistor located adjacently on one side in a direction of row and a drain region of a memory cell transistor located adjacently on the other side in the direction of row, respectively, and the source region and the drain region formed in common, are connected to the bit lines, the dedicated bit line virtual ground type nonvolatile semiconductor storage device comprising:
means for applying a ground potential to the bit line connected to the source region of one memory cell transistor to be subjected to read during read;
means for applying a read drain bias potential to the bit line connected to the drain region of the one memory cell transistor;
means for putting the bit line connected to a source region of a first adjacent memory cell transistor located adjacently on the other side in the direction of row of the one memory cell transistor into a floating state; and
means for applying a potential equal to the read drain bias potential to the bit line connected to a drain region of a second adjacent memory cell transistor located adjacently on the other side in the direction of row of the first adjacent memory cell transistor.
In the virtual ground type nonvolatile semiconductor storage device of this invention, the potential equal to the read drain bias potential is applied to the bit line connected to the drain region of the second adjacent memory cell transistor during the read operation. The bit line connected to the source region of the first adjacent memory cell transistor is in the floating state, and therefore, the source region of the first adjacent memory cell transistor is precharged with the potential equal to the read drain bias potential. Therefore, the leak current from the drain node of the read cell to the adjacent cell is effectively suppressed.
Moreover, lately for the achievement of a high integration density, it is a frequent practice to constitute a block of a plurality of memory cells connected to the bit line (constructed of a diffusion region), interposingly providing a block select transistor at the end portion of each bit line alternately in the direction of row and apply a potential via the block select transistor. In this case, the read cell and the second adjacent memory cell transistor (this being properly referred to as a xe2x80x9csecond adjacent cellxe2x80x9d) are supplied with the potential from the same side in the direction of column. Therefore, the bit line resistance of the read cell and the bit line resistance of the second adjacent cell are substantially the same regardless of the location of the read cell in the array. Therefore, according to the present invention, the potential of the drain region of the read cell and the potential of the drain region of the second adjacent cell substantially become the same during the read operation. Furthermore, the source region of the first adjacent memory cell transistor (this being properly referred to as a xe2x80x9cfirst adjacent cellxe2x80x9d), which is also in the floating state, is therefore precharged with the potential equal to that of the drain region of the read cell and the drain region of the second adjacent cell. Therefore, the leak current from the drain node of the read cell to the first adjacent cell is suppressed regardless of the location of the read cell in the array. Therefore, high-speed read can be achieved in comparison with the conventional case.
In one embodiment, the bit line connected to the source region of the first adjacent memory cell transistor is put into the floating state after being precharged.
In the virtual ground type nonvolatile semiconductor storage device of this one embodiment, the bit line connected to the source region of the first adjacent cell is put into the floating state after being precharged. Therefore, the source region of the first adjacent cell is more rapidly precharged to the potential equal to that of the drain region of the read cell and the drain region of the second adjacent cell. Therefore, the drain node of the read cell can be precharged at higher speed, and more rapid read can be achieved.
One embodiment comprises a sense amplifier, which executes sense amplification upon receiving an input corresponding to a potential change of the bit line connected to the drain region of the one memory cell transistor to be subjected to read; and
a current-to-voltage converter, which converts a change in a current that flows between the source and the drain of the memory cell transistor into a voltage change and inputs the voltage change into the sense amplifier, while suppressing the potential change of the drain region of the memory cell transistor.
In the virtual ground type nonvolatile semiconductor storage device of this one embodiment, during the read operation, the current-to-voltage converter converts the change in the current that flows between the source and the drain regions of the read cell into the voltage change. This sense amplifier executes sense amplification upon receiving this voltage change as an input. In this case, the current-to-voltage converter suppresses the potential change in the drain region of the read cell even when the read cell is in the ON-state (in the low threshold value state). Therefore, almost no potential difference is generated between the drain node of the read cell and the source node of the first adjacent cell. Therefore, the leak current from the first adjacent cell to the read cell is suppressed, and high-speed read can be achieved.
In one embodiment, the plurality of memory cells arranged in a direction of column constitute a block;
a block select transistor is interposedly provided at an end portion of each bit line arranged for each block alternately in the direction of row, and
the block select transistor arranged on one side in the direction of column and the block select transistor arranged on the other side in the direction of column of the block are turned on and off by two control signals which are mutually different every other line in the direction of row.
In the virtual ground type nonvolatile semiconductor storage device of this one embodiment, during the read operation, the block select transistors connected to the source region and the drain region of the read cell are each turned on. The block select transistor connected to the drain region of the first adjacent cell is turned off, while the block select transistor connected to the drain region of the second adjacent cell is turned on. By this operation, the read cell is read.
In this case, the block select transistor connected to the source region of the first adjacent cell can be put into the OFF-state during the precharge operation. Therefore, the load capacity of the bit line connected to the source region of the first adjacent cell becomes owned by only the portion (sub-bit line) arranged in the block. Therefore, the drain node of the first adjacent cell can be precharged very rapidly in comparison with the case where the load capacity of the main bit line (portion that belongs to the bit line and corresponds to the potential supply side of the block select transistor) is added.
Moreover, according to one aspect of this invention, there is provided a bit line control decoder circuit used for a dedicated bit line virtual ground type nonvolatile semiconductor storage device which has a plurality of nonvolatile memory cell transistors arranged in a matrix form, a plurality of word lines for performing row selection and a plurality of bit lines for performing column selection and in which a source region and a drain region of one memory cell transistor are formed in common with a source region of a memory cell transistor located adjacently on one side in a direction of row and a drain region of a memory cell transistor located adjacently on the other side in the direction of row, respectively, and the source region and the drain region formed in common, are respectively connected to the bit lines, the bit line control decoder circuit comprising:
a source bias decoder, which selects a transistor for supplying a source voltage to the bit line connected to the source region of each of the memory cell transistors;
a drain decoder, which selects a drain select transistor (TD0-TD3) by outputting a select signal (D0-D3) to connect the bit line connected to the drain region of each of the memory cell transistors to a sense amplifier; and
a drain bias decoder (DBD), which selects a drain bias select transistor (TC0-TC3) to apply a prescribed voltage to the bit line connected to the drain region of the memory cell transistor, and wherein
the drain bias decoder (DBD) has two groups of drain bias select signal transfer transistors (DD0-DD3, DR0-DR3), which use, every select signal (D0-D3) outputted by the drain decoder, the select signal as a source, and
the drain bias select transistor (TC1), which corresponds to one memory cell transistor, has a gate node connected to the drains of drain bias select signal transfer transistors (DD2, DR0) corresponding to memory cell transistors located next to the one memory cell transistor but one on both sides in the direction of row.
According to the bit line control decoder circuit of this invention, the gate node of the drain bias select transistor (TC1) corresponding to one memory cell transistor is connected to the drains of the drain bias select signal transfer transistors (DD2, DR0) corresponding to the memory cell transistors located next to the one memory cell transistor but one on both sides in the direction of row. Therefore, the drain bias potential equal to that of the bit line connected to the drain of the read circuit can be applied to the bit lines connected to the drains of the memory cell transistors located next to the read circuit but one on both sides in the direction of row. Therefore, the dedicated bit line virtual ground type nonvolatile semiconductor storage device of the above-mentioned invention can produce its operative effects. That is, the leak current from the drain node of the read cell to the first adjacent cell is suppressed regardless of the location of the read cell in the array. Therefore, high-speed read can be achieved in comparison with the conventional case. Furthermore, the bit line control decoder circuit of this invention is constructed comparatively simply without necessitating a substantial increase in the number of transistors.
Moreover, according to one aspect of this invention, there is provided a data read method for a virtual ground type nonvolatile semiconductor storage device, which has a plurality of nonvolatile memory cell transistors arranged in a matrix form, a plurality of word lines for performing row selection and a plurality of bit lines for performing column selection and in which a source region and a drain region of one memory cell transistor are formed in common with a drain region of a memory cell transistor located adjacently on one side in a direction of row and a source region of a memory cell transistor located adjacently on the other side in the direction of row, respectively, and the source and drain regions formed in common, are respectively connected to the bit lines, the data read method comprising the steps of:
applying a ground potential and a read drain bias potential to the bit line connected to the source region and the bit line connected to the drain region, respectively, of one memory cell transistor to be subjected to read, while putting the bit line connected to a drain region of a first adjacent memory cell transistor located adjacently on the other side in the direction of row of the one memory cell transistor into a floating state, and while applying a potential equal to the read drain bias potential to the bit line connected to a drain region of a second adjacent memory cell transistor located adjacently on the other side in the direction of row of the first adjacent memory cell transistor, during read.
According to the data read method of the virtual ground type nonvolatile semiconductor storage device of this invention, the potential equal to the read drain bias potential is applied to the bit line connected to the drain region of the second adjacent memory cell transistor during the read operation. The bit line connected to the drain region of the first adjacent memory cell transistor is in the floating state. Accordingly, the drain region of the first adjacent memory cell transistor is precharged with the potential equal to the read drain bias potential. Therefore, the leak current from the drain node of the read cell to the adjacent cell is effectively suppressed.
Moreover, lately for the achievement of a high integration density, it is a frequent practice to constitute a block of a plurality of memory cells connected to the bit line (constructed of a diffusion region), interposingly providing a block select transistor at the end portion of each bit line alternately in the direction of row and apply a potential via the block select transistor. In this case, the read cell and the second adjacent memory cell transistor (this being properly referred to as a xe2x80x9csecond adjacent cellxe2x80x9d) are supplied with the potential from the same side in the direction of column. Therefore, the bit line resistance of the read cell and the bit line resistance of the second adjacent cell are substantially the same regardless of the location of the read cell in the array. Therefore, according to the present invention, the potential of the drain region of the read cell and the potential of the drain region of the second adjacent cell substantially become the same during the read operation. Furthermore, the drain region of the first adjacent memory cell transistor (this being properly referred to as a xe2x80x9cfirst adjacent cellxe2x80x9d), which is also in the floating state, is therefore precharged with the potential equal to that of the drain region of the read cell and the drain region of the second adjacent cell. Therefore, the leak current from the drain node of the read cell to the first adjacent cell is suppressed regardless of the location of the read cell in the array. Therefore, high-speed read can be achieved in comparison with the conventional case.
Moreover, according to one aspect of this invention, there is provided a data read method for a dedicated bit line virtual ground type nonvolatile semiconductor storage device, which has a plurality of nonvolatile memory cell transistors arranged in a matrix form, a plurality of word lines for performing row selection and a plurality of bit lines for performing column selection and in which a source region and a drain region of one memory cell transistor are formed in common with a source region of a memory cell transistor located adjacently on one side in a direction of row and a drain region of a memory cell transistor located adjacently on the other side in the direction of row, respectively, and the source region and the drain region formed in common, are respectively connected to the bit lines, the data read method comprising the steps of:
applying a ground potential and a read drain bias potential to the bit line connected to the source region and the bit line connected to the drain region, respectively, of one memory cell transistor to be subjected to read, while putting the bit line connected to a source region of a first adjacent memory cell transistor located adjacently on the other side in the direction of row of the one memory cell transistor into a floating state, and while applying a potential equal to the read drain bias potential to the bit line connected to a drain region of a second adjacent memory cell transistor located adjacently on the other side in the direction of row of the first adjacent memory cell transistor, during read.
According to the data read method of the virtual ground type nonvolatile semiconductor storage device of this invention, the potential equal to the read drain bias potential is applied to the bit line connected to the drain region of the second adjacent memory cell transistor during the read operation. The bit line connected to the source region of the first adjacent memory cell transistor is in the floating state. Accordingly, the source region of the first adjacent memory cell transistor is precharged with the potential equal to the read drain bias potential. Therefore, the leak current from the drain node of the read cell to the adjacent cell is effectively suppressed.
Moreover, lately for the achievement of a high integration density, it is a frequent practice to constitute a block of a plurality of memory cells connected to the bit line (constructed of a diffusion region), interposingly providing a block select transistor at the end portion of each bit line alternately in the direction of row and apply a potential via the block select transistor. In this case, the read cell and the second adjacent memory cell transistor (this being properly referred to as a xe2x80x9csecond adjacent cellxe2x80x9d) are supplied with the potential from the same side in the direction of column. Therefore, the bit line resistance of the read cell and the bit line resistance of the second adjacent cell are substantially the same regardless of the location of the read cell in the array. Therefore, according to the present invention, the potential of the drain region of the read cell and the potential of the drain region of the second adjacent cell substantially become the same during the read operation. Furthermore, the source region of the first adjacent memory cell transistor (this being properly referred to as a xe2x80x9cfirst adjacent cellxe2x80x9d), which is also in the floating state, is therefore precharged with the potential equal to that of the drain region of the read cell and the drain region of the second adjacent cell. Therefore, the leak current from the drain node of the read cell to the first adjacent cell is suppressed regardless of the location of the read cell in the array. Therefore, high-speed read can be achieved in comparison with the conventional case.